Neuromorphic circuits are networks of multiple cells, configured in such a way as to somewhat imitate the behaviour of biological neuronal networks. Biological neuronal networks comprise elementary neurons which receive and emit information, and synapses which connect these neurons to other neurons. By analogy, the neuromorphic circuits generally comprise a matrix network of elementary processing cells that will be called neurons, each identified by a respective address in the memory, and a matrix memory with as many elementary memories as there are neurons; each elementary memory is associated with a neuron and can therefore be identified by the unique address of this neuron; it contains addresses of other neurons which have to receive information from the neuron corresponding to this elementary memory.
Hereinbelow, the so-called “discharging” neurons will be considered. These neurons receive input signals from other neurons; they process them in generally analogue form and produce a result. The result can be the emission of an event signal, for example a pulse at a given moment. It is this pulse, called “neuron discharge”, which is used to fetch from the elementary memory associated with the neuron not only the addresses of other neurons (target neurons or destination neurons), but also weights associated with each of these addresses. The associated weights signify that a neuron will influence one or more other neurons in a weighted manner and not in an undifferentiated manner.
The addresses of the neurons influenced by a neuron are called post-synaptic addresses; the associated weights are called synaptic weights.
For example, an analogue elementary neuron may be constructed in the form of a time integrator with leakage; its internal potential represents the algebraic sum of several potentials applied over time to its inputs by other neurons, this sum being affected by leakage currents; when the internal potential reaches a certain threshold, the neuron signals this event by emitting an event signal which is a pulse of very short duration, often called “spike”. The potential then reverts to an idle state, awaiting new inputs. The event signal, or spike, is used, with the address of the neuron which has emitted it, to extract the content of the elementary memory associated with this address; this content is made up of one or more post-synaptic addresses and their associated synaptic weights. These addresses and weights are received by a processing circuit which generates weighted input signals and which transmits them as input signals to the neurons corresponding to the post-synaptic addresses.
In the prior art as illustrated in FIG. 1, the event signal deriving from the discharge of a neuron from the neuronal matrix RN is applied to an address encoder ENC which determines the address of the neuron which has generated the event and which sends this address over a so-called pre-synaptic bus Bpre-syn. The pre-synaptic bus is an address bus for the memory. This bus is managed by a controller CTRL which applies this address to the memory MEM and which collects from the memory one or more post-synaptic addresses and the weights associated with each of them. The controller successively emits the different post-synaptic addresses over a post-synaptic address bus Bpost-syn which applies these addresses to an address decoder DEC associated with the neuronal matrix RN. At the same time, the controller sends the synaptic weights to a digital-to-analogue converter DAC which establishes analogue levels as a function of each synaptic weight. An analogue signal level corresponding to a determined synaptic weight is therefore applied to each of the post-synaptic neurons identified by the content of the elementary memory which has been activated by the event signal.
The neuron can be schematically represented as in FIG. 2 by a capacitive node ND, of capacitance Cnd. This node is connected to the input of a threshold comparator CMP. The input of the neuron consists of a terminal E linked to the node ND; this is a current input and the input current is used to charge (or discharge) the capacitance. For example, a current pulse of determined time width, positive or negative, of amplitude representing a synaptic weight, is applied to the input E each time the neuron is designated by another neuron. Moreover, the capacitive node may exhibit leaks so that the capacitance of the node is discharged progressively if new charge pulses do not arrive at the input E. When the voltage at the terminals of the capacitance increases sufficiently to reach the threshold of the comparator, the latter emits a brief pulse which is the event signal or spike from the neuron.
FIG. 3 represents a post-synaptic neuron which has been designated by the post-synaptic bus and which can then receive from the digital-to-analogue converter DAC an analogue signal whose amplitude represents a synaptic weight. This signal is a brief current pulse. The synaptic weight Pds is contained in digital form in the memory MEM, at the address of the neuron (pre-synaptic) which has emitted a spike to the post-synaptic neuron considered here. The digital-to-analogue converter converts this digital weight into an analogue current value emitted during a pulse of predefined duration.
Numerous embodiments of digital-to-analogue converters exist, but it is important to produce the converter in a particularly simple form. The aim of the invention is to propose a digital-to-analogue converter which is of simple construction and has little bulk, which can be used more particularly in this neuromorphic circuit application.